The present invention relates to electronic circuits, and in particular to electronic circuits for performing logic operations.
Logic circuits have a wide variety of uses and may be configured to perform arithmetical operations. A basic full adder circuit can be described by the following two equations:Sum=A⊕B⊕Cin  (Eq. 1)Cout=AB+BCin+ACin  (Eq. 2)
A full adder cell or block can be illustrated in the form shown in FIG. 1. The full adder cell 1 has first and second inputs 3, 5 for receiving the numbers (A, B) to be summed, a carry input 7, a carry output 9 and a sum output 11. Typically each input and output is a single bit. In order to perform higher order addition, a number of full adders are connected together in a series with the carry output of one adder being connected to the carry input of another adder. An example of a four-bit adder circuit is shown in FIG. 2 and comprises four full adder cells 2, 4, 6 and 8. The main concerns in designing a full adder circuit are the speed and area of the circuit. In the four-bit full adder shown in FIG. 2, the maximum propagation delay can be described by:4bit_delay=tH+4×tcarry+tSum  (Eq. 3)where tH describes the delay through the circuit that implements (Eq. 4) logic:H=ĀB+A B=A⊕B  (Eq.4)Using (Eq.4), (Eq.1) and (Eq.2) are rewritten as:Sum=H⊕Cin  (Eq. 5)Cout= HA+HCin  (Eq. 6)tcarry describes the delay from Cin to Cout of a full adder cell, and tSum describes the delay through the circuit that implements Eq. 5. The reason that the H-equation logic is added is to minimize the number of input lines that effect the propagation of Cin to Cout.
FIG. 3 shows a typical standard cell implementation of a full adder which implements equations 4, 5 and 6. The adder circuit comprises a first (or input) XOR gate 15 for determining the value of H (equation 3), an inverter 17 at the output of the XOR gate 15 for deriving the value H for use in equation 6, a first transmission gate 19, a carry propagate circuit 21 (transmission means) between the carry input and carry output 7, 9, and a summing circuit 31 comprising a second XOR gate for implementing equation 5. The carry propagate circuit 21 comprises a second transmission gate 23 and a buffer 25 comprising a pair of serially arranged inverters 27, 29.
The first input 20 of the first transmission gate 19 is connected to the first input 3 of the adder circuit and the other complementary inputs 22, 24 (NMOS gate and PMOS gate) are connected to receive the values H and H respectively. The output 26 of the first transmission gate 19 is connected to the carry propagate circuit 21 and implements the first term of equation 6. The first input 28 of the second transmission gate 23 is connected to the C input 7 of the carry propagate circuit and the complementary inputs 30, 32 are connected to receive the values of H and H, respectively. The output 34 of the second transmission gate outputs the value HCIN which is the second term of equation 6.
One of the inputs 36 of the second (or summing) XOR gate 31 is connected to the output of the first XOR gate 15 for receiving the value H and the second input 38 of the second XOR gate is connected to the input 7 of the carry propagate circuit 21 for receiving the value CIN.
The components of the full adder circuit shown in FIG. 3 that are responsible for the propagation delay of equation 3 are as follows. tH is the delay through the input XOR gate 15, tSUM is the delay through the output XOR gate 31, and tCARRY is the delay from CIN to COUT (for bit 0 this might be from the first input 3 (A) to COUT). It is apparent from equation 3 that the propagation delay from CIN to COUT in a multiple cell adder is more heavily weighted than other parts of the equation, and this delay plays a pivotal role in determining the total delay through the adder chain.
In a typical standard cell implementation, when H=1, the CIN signal is loaded by the gate capacitance of the second XOR gate 31, which is equal to, at the very least, the input capacitance of an inverter comprising an N-type and P-type gate capacitance; the N-type and P-type gate capacitance of the second transmission gate 23, the two drain to gate capacitances of the first transmission gate 19 and the input capacitance of the buffer cell 25. In addition, there is a propagation delay through the output buffer cell, which comprises two inverters 27, 29 in series.
It would be desirable to reduce the propagation delay in the carry propagate circuit.